ASIC'16 One day Hands on Training In ASIC DESIGN FLOW, April 2016, VIT University, Vellore, Tamilnadu, India

College/University/Organization Name: VIT University
Organizing Department: School of Electronics Engineering
Event Date: 04/16/2016 -- 04/16/2016    (MM/DD/YYYY)
Last Date: 04/11/2016    (MM/DD/YYYY)
Address: Vellore, Tamilnadu, India

Registration Fee:

For Faculty/Industry Person - Rs. 1500/-
For Students/Research Scholars – Rs. 1100/-

College/University/Organization Website:

Email Address:

About Event:

Basic ASIC Flow

  • Basic Timing Analysis
  • Advanced static timing Analysis
  • Optimal Floor plan Designs
  • Physical Optimization
  • technique – for Placement &
  • Clock tree synthesis
  • Physical Implementation -
  • Routing and Design Rule Check
  • (DRC)
  • Hands on with simple Example.

Who Can Participate?

Students interested in VLSI Design.
Faculties, Industry Persons, Research Scholars

Accommodation Details:


Other Details:

Mr. Muthukumaravel Sachidanandam
Senior Staff Design Engineer,
Applied Micro. Inc,

Mr. Rajesh S.
Staff Design Engineer,
Applied Micro. Inc,

you can register through this link given below

Contact Details:
Prof. R. Dhanbal, Assistant Professor Sr,
Dept. of Micro & Nanoelectronics,
School of Electronics Engineering,
VIT University,
Vellore – 632014,

For any clarification about this event, please contact the above mentioned address.

One day Hands on Training In ASIC DESIGN FLOW-2016-VIT University-Vellore-Tamilnadu-India

See Also