Organizing Department: School of Electronics Engineering
Event Date: 04/16/2016 -- 04/16/2016
(MM/DD/YYYY)
Last Date: 04/11/2016 (MM/DD/YYYY)
Address: Vellore, Tamilnadu, India
Registration Fee:
For Faculty/Industry Person - Rs. 1500/-
For Students/Research Scholars – Rs. 1100/-
For Students/Research Scholars – Rs. 1100/-
College/University/Organization
Website: www.vit.ac.in
Event Website / Brochure link:
http://www.vit.ac.in/events/eventView/One%20day%20Hands%20on%20Training%20In%20ASIC%20Design%20Flow
Email Address: ranitha@vit.ac.in
About Event:
Basic ASIC Flow
- Basic Timing Analysis
- Advanced static timing Analysis
- Optimal Floor plan Designs
- Physical Optimization
- technique – for Placement &
- Clock tree synthesis
- Physical Implementation -
- Routing and Design Rule Check
- (DRC)
- Hands on with simple Example.
Who Can Participate?
Students interested in VLSI Design.
Faculties, Industry Persons, Research Scholars
Faculties, Industry Persons, Research Scholars
Accommodation Details:
No
Other Details:
RESOURCE PERSONS:
Mr. Muthukumaravel Sachidanandam
Senior Staff Design Engineer,
Applied Micro. Inc,
Bangalore
Mr. Rajesh S.
Staff Design Engineer,
Applied Micro. Inc,
Bangalore
you can register through this link given below
http://tinyurl.com/jhtzcmo
Contact Details:
Prof. R. Dhanbal, Assistant Professor Sr,
Dept. of Micro & Nanoelectronics,
School of Electronics Engineering,
VIT University,
Vellore – 632014,
TamilNadu.
ranitha@vit.ac.in
rdhanabal@vit.ac.in
9443030999
Dept. of Micro & Nanoelectronics,
School of Electronics Engineering,
VIT University,
Vellore – 632014,
TamilNadu.
ranitha@vit.ac.in
rdhanabal@vit.ac.in
9443030999
For any clarification about
this event, please contact the above mentioned address.
One day Hands
on Training In ASIC DESIGN FLOW-2016-VIT University-Vellore-Tamilnadu-India
See Also