International Conference on Innovations in Electrical, Information and Communication Engineering
Annexure 1 and Annexure 2 Publication
All the paper will be published in International Journals

Two day Workshop and Hands-on Training on UVM for Verilog based VLSI Applications, July 2016, VIT University, Vellore, Tamilnadu, India


College/University/Organization Name: VIT University
Organizing Department: School of Electrical Engineering
Event Date: 07/22/2016 -- 07/23/2016    (MM/DD/YYYY)
Last Date: 07/20/2016    (MM/DD/YYYY)
Address: Vellore, Tamilnadu, India

Registration Fee:

Faculty/Engineers: Rs.2500
Students/ Research scholars:Rs. 1500

College/University/Organization Website: www.vit.ac.in


Email Address: umasathyakam.p@vit.ac.in

About Event:

Go2UVM – the fastest way to get started with the semiconductor industry’s most adopted verification methodology (UVM): Go2UVM is the preferred way for industry engineers running DFT and other related verification traces back in simulation domain. For students and budding engineers, Go2UVM provides the ideal starting point to write quality simulation traces with UVM and thereby making them most appealing and wanted by the semiconductor design houses looking to hire them from the universities.

Who Can Participate?

Faculty members
Engineers from industries
UG, PG students and Research Scholars

Accommodation Details:

Yes. Will be provided in hostels.

Other Details:

Workshop is organized by VIT University in Collaboration with CVC pvt. Ltd., Bangalore - a VLSI company.
Resource persons are from CVC pvt. Ltd.

Contact Details:
Mr. P. Uma Sathyakam,
Mobile: 9962115704
Email: umasathyakam.p@vit.ac.in
Mr. A. Karthikeyan
Mobile: 9884725721,
Email: karthikeyan.arun@vit.ac.in


For any clarification about this event, please contact the above mentioned address.

Two day Workshop and Hands-on Training on UVM for Verilog based VLSI Applications-2016-VIT University-Vellore-Tamilnadu-India

See Also