FDTP'16 FACULTY DEVELOPMENT & TRAINING PROGRAMME, DECEMBER 2016, TRP ENGINEERING COLLEGE (SRM Group), TRICHY, Tamilnadu, India


College/University/Organization Name: TRP ENGINEERING COLLEGE(SRM Group)
Organizing Department: ECE
Event Date: 12/01/2016 -- 12/02/2016    (MM/DD/YYYY)
Last Date: 11/28/2016    (MM/DD/YYYY)
Address: TRICHY, Tamilnadu, India

Registration Fee:

Registration Fee: Rs.400/- per participant.



College/University/Organization Website: www.trpengg.ac.in

Event Website / Brochure link: www.trpengg.ac.in

Email Address: trpec.ece@gmail.com

About Event:

PROGRAM HIGHLIGHTS
     Basics of VLSI Design Analysis and Design of
          Combinational Logic Circuit
          Sequential Logic Circuit Design
          Adders, Multipliers and Dividers
          Introduction to VHDL & Verilog HDL


Who Can Participate?

Faculty teaching VLSI related courses and Research Scholars in the field of VLSI from various Engineering Colleges with relevant backround can apply. The number of participants is limited to 60.

Accommodation Details:

yes,inform two days before


Other Details:

HANDS ON TRAINING ON

          Research Opportunities in the field of VLSI
          Differential Amplifier Design and ASIC Design using     Cadence/Tanner Tool.
          Low Power Circuit Design
          ASIC and FPGA Design Principles


Contact Details:
MAILING ADDRESS:
                      
      The HOD,
      Department  of ECE,
      TRP Engineering College
      (SRM Group),
      Irungalur, Mannachanallur- Taluk,
      Tiruchirappalli, Tamilnadu– 621 105.

CONTACT US

Website  : http://www.trpengg.ac.in
Email      : trp.hodece@srmcampus.org;
                  trpec.ece@gmail.com
Mobile    : 9655431075, 9487332465&
                  9698126661


For any clarification about this event, please contact the above mentioned address.

FACULTY DEVELOPMENT & TRAINING PROGRAMME-2016-TRP ENGINEERING COLLEGE(SRM Group)-TRICHY-Tamilnadu-India

See Also