Organizing Department: Department of Electronics and Communication Engineering
Event Date: 03/09/2017 -- 03/10/2017
(MM/DD/YYYY)
Last Date: 03/06/2017 (MM/DD/YYYY)
Address: Coimbatore , Tamilnadu, India
Registration Fee:
Research Scholars, UG/PG Students , Industry / R&D
organizations &
Faculty from Academic Institutions: RS. 400-
Faculty from Academic Institutions: RS. 400-
College/University/Organization Website: https://www.srec.ac.in
Event Website / Brochure link:
https://www.srec.ac.in
Email Address: manikandababu.shelvaraju@srec.ac.in
About Event:
The participants will gain hands-on experience on ALTERA FPGA
Design flow and Oops concept of System Verilog.
Who Can Participate?
Participants
: Research Scholars, UG/PG Students , Industry / R&D organizations
&
Faculty from Academic Institutions
Faculty from Academic Institutions
Accommodation Details:
Is available
on chargeable basis, on request.
Other Details:
Contact Details:
9994158642
For any clarification about
this event, please contact the above mentioned address.
Two day
National Workshop on 'VLSI Front End Design – SoC System Design
Process'-2017-Sri Ramakrishna Engineering College,Coimbatore -Coimbatore
-Tamilnadu-India
See Also
NIL -Coimbatore -2017-Sri Ramakrishna Engineering College,Coimbatore
-tamilnadu