College/University/Organization
Name: K.RAMAKRISHNAN COLLEGE OF TECHNOLOGY
Organizing Department: ECE
Event Date: 03/23/2016 -- 03/24/2016
(MM/DD/YYYY)
Last Date: 03/16/2016 (MM/DD/YYYY)
Address: TRICHY, Tamilnadu, India
Registration Fee:
1000/PER PARTCIPANT
College/University/Organization
Website: www.krct.ac.in
Event Website / Brochure link: www.krct.ac.in
Email Address: rajendra1987kumar@gmal.com
About Event:
Very-large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining thousands of transistors into a single
chip. Before the introduction of VLSI technology most ICs had a limited set of
functions they could perform. An electronic circuit might consist of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one
chip. To accommodate all these things in single IC is not possible with manual
handling, so we are moving to the Electronic Design Automation (EDA) Tools.
Cadence is such a tool to design the layouts of IC, for manufacturing millions
of ICs.
A cadence custom IC design solution automates many of the routine tasks involved in Custom IC Design, allowing engineers to focus on differentiating their designs.
Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit design solutions enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware environment, you can abstract and visualize the many interdependencies of an analog, RF, or mixed-signal design to understand and determine their effects on circuit performance.
Who Can Participate?
UG / PG Scholars
Researchers in VLSI domain
Faculties from ECE Department
Researchers in VLSI domain
Faculties from ECE Department
Accommodation Details:
NO ACCOMMODATION WILL BE PROVIDED
Other Details:
Verilog/VHDL
Simulation
Netlist Creation
SOC Layout Generation
Analog Simulation
Layout creation, DRC
LVS and RC Extraction
Post layout simulation and GDSII Generation
Basics of Mixed signal design
SPICE Simulation
Netlist Creation
SOC Layout Generation
Analog Simulation
Layout creation, DRC
LVS and RC Extraction
Post layout simulation and GDSII Generation
Basics of Mixed signal design
SPICE Simulation
Contact Details:
The Coordinator,
Department of ECE,
K.Ramakrishnan College of Technology,
Samayapuram, Trichy – 621 112.
Phone No.:9944564969,9003737966
Department of ECE,
K.Ramakrishnan College of Technology,
Samayapuram, Trichy – 621 112.
Phone No.:9944564969,9003737966
For any clarification about
this event, please contact the above mentioned address.
TWO DAYS
WORKSHOP ON CIC & ASIC FLOW DESIGN ON CADENCE -2016-K.RAMAKRISHNAN COLLEGE
OF TECHNOLOGY-TRICHY-Tamilnadu-India
See Also