Organizing Department: School of Electrical Engineering
Event Date: 03/17/2017 -- 03/18/2017
(MM/DD/YYYY)
Last Date: 03/10/2017 (MM/DD/YYYY)
Address: Vellore, Tamilnadu, India
Registration Fee:
Registration fee
Faculty/Engineers: Rs. 2000
Students/ Research scholars: Rs. 1000
Faculty/Engineers: Rs. 2000
Students/ Research scholars: Rs. 1000
College/University/Organization Website: http://info.vit.ac.in/conference/SDSP/apply.asp
Event Website / Brochure link:
http://info.vit.ac.in/conference/SDSP/apply.asp
Email Address: asharmila@vit.ac.in
About Event:
This workshop is intended to provide an overview of theoretical
and mathematical knowledge on signals, systems and digital signals processing
for undergraduate, graduate students and research scholars of various
disciplines. After the successful completion on this workshop, the participants
will be able to apply mathematical and theoretical knowledge in their
respective field. This workshop will take along great exposure to the
participants who are working in the field of signal processing and control
domain.
Who Can Participate?
Students/Research
Scholars and facultiies
Accommodation Details:
Yes
Other Details:
Contact Details:
Prof. V.
Sankardoss
Assistant Professor (Senior)
School of Electrical Engineering
VIT University, Vellore-632 014.
91+9095174226, vsankardoss@vit.ac.in
Prof. A. Sharmila
Assistant Professor
School of Electrical Engineering
VIT University, Vellore-632 014.
91+ 9487556692, asharmila@vit.ac.in.
Assistant Professor (Senior)
School of Electrical Engineering
VIT University, Vellore-632 014.
91+9095174226, vsankardoss@vit.ac.in
Prof. A. Sharmila
Assistant Professor
School of Electrical Engineering
VIT University, Vellore-632 014.
91+ 9487556692, asharmila@vit.ac.in.
For any clarification about
this event, please contact the above mentioned address.
Two day
Workshop on An Overview of Signals, Systems and Digital Signal
Processing-2017-VIT University-Vellore-Tamilnadu-India
See Also
SSDSP'17-Vellore-2017-VIT University-tamilnadu